Design and emulation of new robust architectures for UHF RFID Tags

RFID ICs such as EPC gen2 tag are low cost tags which can be used for critical or secure applications. Increasing their robustness is not trivial due to the wide range of error sinks (EM perturbation, attacks...). Moreover increasing the robustness must have a minimum impact on the die area but also must fit with a standardized protocol. In this work we propose a design methodology in order to develop hardened EPC architecture with a dedicated verification environment taking into account all RFID system parameter. KeywordsFault Injection, RFID Security, RFID attacks, FPGA prototype, Secure IC, Robust IC, EPC .